NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 799
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
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Compliant
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Thermal Sensor Registers (D31:F6)
21.2.4
21.2.5
21.2.6
Intel
®
ICH8 Family Datasheet
TSxCO—Thermal Sensor [1:0] Catastrophic Lock-Down
Offset Address:
Default Value:
TSxPC—Thermal Sensor [1:0] Policy Control
Offset Address:
Default Value:
TSxLOCK—Thermal Sensor [1:0] Register Lock Control
Offset Address:
Default Value:
6:0
5:0
7:3
1:0
Bit
Bit
Bit
7
7
6
2
Lock bit for Catastrophic (LBC) — R/W. This bit may only be set to a 0 by a hardware reset.
Writing a 0 to this bit has no effect.
1 = Locks the Catastrophic programming interface including TSxTTP.bits[7:0].
0 = Catastrophic programming interface is unlocked
Reserved
Policy Lock-Down Bit — R/W. This bit may only be set to a 0 by a hardware reset. Writing a 0 to
this bit has no effect.
1 = Prevents writes to this register.
0 = This register can be programmed and modified.
NOTE: TSxCO.bit 7 and TSxLOCK.bit 2 must also be 1 when this bit is set to 1.
Catastrophic Power-Down Enable — R/W.
0 = Disable
1 = Enable. Power management logic unconditionally transitions to the S5 state when
Reserved
Reserved
Lock Control — R/W. This bit must be set to 1 when TSxPC.bit7 is set to 1.
Reserved
a catastrophic temperature is detected by the sensor.
Sensor 0: TBARB+08h
Sensor 1: TBARB+48h
00h
Sensor 0: TBARB+0Eh
Sensor 1: TBARB+4Eh
00h
Sensor 0: TBARB+83h
Sensor 1: TBARB+C3h
00h
§ §
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bit
R/W
8 bit
R/W
8 bit
799
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