NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 593

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7, D26:F7)
15.1.18
Intel
®
ICH8 Family Datasheet
PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 52h
Default Value:
NOTES:
1.
2.
15:11
8:6
2:0
Bit
10
9
5
4
3
Normally, this register is read-only to report capabilities to the power management
software. To report different power management capabilities, depending on the system in
which the ICH8 is used, bits 15:11 and 8:6 in this register are writable when the
WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set. The value written to this register
does not affect the hardware other than changing the value returned during a read.
Reset: core well, but not D3-to-D0 warm reset.
PME Support (PME_SUP) — R/W (special). This 5-bit field indicates the power states
in which the function may assert PME#. The Intel
or D2 states. For all other states, the ICH8 EHC is capable of generating PME#.
Software should never need to modify this field.
D2 Support (D2_SUP) — RO.
0 = D2 State is not supported
D1 Support (D1_SUP) — RO.
0 = D1 State is not supported
Auxiliary Current (AUX_CUR) — R/W (special). The ICH8 EHC reports 375 mA
maximum suspend well current required when in the D3
Device Specific Initialization (DSI)— RO. The ICH8 reports 0, indicating that no
device-specific initialization is required.
Reserved
PME Clock (PME_CLK) — RO. The ICH8 reports 0, indicating that no PCI clock is
required to generate PME#.
Version (VER) — RO. The ICH8 reports 010b, indicating that it complies with Revision
1.1 of the PCI Power Management Specification.
C9C2h
–
53h
Description
Attribute:
Size:
®
ICH8 EHC does not support the D1
COLD
R/W (special), RO
16 bits
state.
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