NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 474
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
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12.1.15.2
12.1.16
12.1.17
12.1.18
474
When CC.SCC is 01h
Address Offset: 24h
Default Value:
When the programming interface is IDE, the register becomes an I/O BAR allocating
16 bytes of I/O space for the I/O-mapped registers defined in
although 16 bytes of locations are allocated, only 8 bytes are used to as SINDX and
SDATA registers; with the remaining 8 bytes preserved for future enhancement.
SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset: 2Ch
Default Value:
Lockable:
SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh
Default Value:
Lockable:
CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h
Default Value:
31:16
15:0
15:0
15:4
7:0
3:1
Bit
Bit
Bit
Bit
0
Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is
80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in
configuration space indicates that the SATA function and PATA functions are combined
(values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE
mode (value of 01).
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware
action taken on this value.
Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
Reserved
Base Address (BA) — R/W. Base address of the I/O space.
Reserved
Resource Type Indicator (RTE) — RO. Indicates a request for I/O space.
00000001h
0000h
No
0000h
No
80h
–
–
–
27h
2Fh
2Dh
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
SATA Controller Registers (D31:F2)
Section
R/WO
32 bits
R/WO
16 bits
Core
R/WO
16 bits
Core
RO
8 bits
Intel
®
ICH8 Family Datasheet
12.3. Note that
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