NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 270
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 270 of 890
- Download datasheet (7Mb)
7.1.7
7.1.8
270
V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h
Default Value:
V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 001A–001Bh
Default Value:
30:27
26:24
23:20
19:17
15:02
15:8
7:1
Bit
Bit
31
16
0
1
0
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and
cannot be disabled.
Reserved
Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual channel.
Reserved
Port Arbitration Select (PAS) — R/W. Indicates which port table is being
programmed. The root complex takes no action on this setting since the arbitration is
fixed and there is no arbitration table.
Load Port Arbitration Table (LAT) — RO. The root complex does not implement an
arbitration table for this virtual channel.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
Reserved
VC Negotiation Pending (NP) — RO. When set, indicates the virtual channel is still
being negotiated with ingress ports.
Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for this
VC, so this bit is reserved at 0.
800000FFh
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
R/W, RO
32-bit
RO
16-bit
Intel
®
ICH8 Family Datasheet
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