NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 198

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NH82801HEM S LA5R

Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LA5R

Lead Free Status / RoHS Status
Compliant
5.16.2
Note:
5.16.3
198
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
If software clears bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
SATA Swap Bay Support
Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SATA host controller
without special support from AHCI and the proper board hardware. However, the ICH8
does provide for basic SATA swap bay support using the PSC register configuration bits
and power management flows. A device can be powered down by software and the port
can then be disabled, allowing removal and insertion of a new device.
This SATA swap bay operation requires board hardware (implementation specific),
BIOS, and operating system support.
Intel
ICH8R, ICH8DH, ICH8DO, and ICH8M-E Only)
The Intel
(redundant array of independent disks) to meet the needs of the end user. AHCI
support provides higher performance and alleviates disk bottlenecks by taking
advantage of the independent DMA engines that each SATA port offers in ICH8.
By using the ICH8’s built-in Intel Matrix Storage Technology, there is no loss of PCI
resources (request/grant pair) or add-in card slot.
Intel
Intel Matrix Storage Technology is not available in the following configurations:
1. ICH8 component enabled for Intel Matrix Storage Technology (see
2. Intel
3. Intel
4. At least two SATA hard disk drives (minimum depends on RAID configuration).
1. The SATA controller in compatible mode.
• RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for
• Data security is offered through RAID Level 1, which performs mirroring.
• RAID Level 10 provides high levels of storage performance with data protection,
• RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on
data intensive applications such as video editing.
combining the fault-tolerance of RAID Level 1 with the performance of RAID Level
0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems
that require both performance and fault-tolerance. RAID Level 10 requires 4 hard
drives, and provides the capacity of two drives.
3 or more drives. By striping parity, and rotating it across all disks, fault tolerance
of any single drive is achieved while only consuming 1 drive worth of capacity. That
is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the
capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write
rate. RAID 5 is well suited for applications that require high amounts of storage
while maintaining fault tolerance.
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Matrix Storage Technology functionality requires the following items:
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Matrix Storage Technology Configuration (Intel
Matrix Storage Manager RAID Option ROM must be on the platform
Matrix Storage Manager drivers, most recent revision.
Matrix Storage Technology offers several diverse options for RAID
Intel
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Functional Description
ICH8 Family Datasheet
Section
1.2)
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