NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 288
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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7.1.52
288
D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h
Default Value:
31:16
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Bit
Reserved
Thermal Throttle Pin (TTIP) — R/W. This field indicates which pin the Thermal
Throttle controller drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin 2 (SIP2) — R/W. This field indicates which pin the SATA controller 2
drives as its interrupt.
0h = No interrupt.
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Reserved
SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller
drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as
its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
PATA Pin (SMIP) — R/W. This field indicates which pin the PATA controller drives as
its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
LPC Bridge Pin (PIP) — RO. Currently, the LPC bridge does not generate an interrupt,
so this field is read-only and 0.
03243210h
Description
Attribute:
Size:
Chipset Configuration Registers
R/W, RO
32-bit
Intel
®
ICH8 Family Datasheet
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