NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 327
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 327 of 890
- Download datasheet (7Mb)
LPC Interface Bridge Registers (D31:F0)
9.1.7
9.1.8
9.1.9
9.1.10
Intel
®
ICH8 Family Datasheet
SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah
Default Value:
BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh
Default Value:
PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh
Default Value:
HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh
Default Value:
7:0
7:0
7:3
2:0
6:0
Bit
Bit
Bit
Bit
7
Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC
bridge.
01h = PCI-to-ISA bridge.
Base Class Code — RO. 8-bit value that indicates the type of device for the LPC
bridge.
06h = Bridge device.
Master Latency Count (MLC) — Reserved.
Reserved.
Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration
space.
01h
06h
00h
80h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
327
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