NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 179

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
Table 73.
5.13.10.2
Intel
Addr
I/O
08h
20h
®
ICH8 Family Datasheet
# of
Rds
12
6
Access
Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
NOTES:
1.
2.
PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in
10
11
12
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
Restore Data
The OCW1 register must be read before entering ALT access mode.
Bits 5, 3, 1, and 0 return 0.
DMA Chan 0–3 Command
DMA Chan 0–3 Request
DMA Chan 0 Mode:
Bits(1:0) = 00
DMA Chan 1 Mode:
Bits(1:0) = 01
DMA Chan 2 Mode:
Bits(1:0) = 10
DMA Chan 3 Mode: Bits(1:0) =
11.
PIC ICW2 of Master controller
PIC ICW3 of Master controller
PIC ICW4 of Master controller
PIC OCW1 of Master
controller
PIC OCW2 of Master controller
PIC OCW3 of Master controller
PIC ICW2 of Slave controller
PIC ICW3 of Slave controller
PIC ICW4 of Slave controller
PIC OCW1 of Slave controller
PIC OCW2 of Slave controller
PIC OCW3 of Slave controller
1
Data
Table
2
74.
1
Addr
I/O
CAh
CCh
D0h
CEh
# of
Rds
2
2
2
6
Access
1
2
1
2
1
2
1
2
3
4
5
6
Restore Data
DMA Chan 6 base count low
byte
DMA Chan 6 base count high
byte
DMA Chan 7 base address low
byte
DMA Chan 7 base address
high byte
DMA Chan 7 base count low
byte
DMA Chan 7 base count high
byte
DMA Chan 4–7 Command
DMA Chan 4–7 Request
DMA Chan 4 Mode: Bits(1:0)
= 00
DMA Chan 5 Mode: Bits(1:0)
= 01
DMA Chan 6 Mode: Bits(1:0)
= 10
DMA Chan 7 Mode: Bits(1:0)
= 11.
Data
2
179