NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 785

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (SPI)
20.3.13
Note:
Intel
®
ICH8 Family Datasheet
SSFS—Software Sequencing Flash Status Register
(
Memory Address:GLBAR + 90h
Default Value:
The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
GbE LAN Memory Mapped Configuration Registers
7:5
Bit
4
3
2
1
0
Reserved
Access Error Log (AEL): — RO. This bit reflects the value of the Hardware
Sequencing Status AEL register.
Flash Cycle Error (FCERR): — R/WC. Hardware sets this bit to 1 when a programmed
access is blocked from running on the SPI interface due to one of the protection policies
or when any of the programmed cycle registers is written while a programmed access is
already in progress. This bit remains asserted until cleared by software writing a 1 or
hardware reset.
Hardware reset is initiated by one of the following resets:
Cycle Done Status: — R/WC. The ICH8 sets this bit to 1 when the SPI Cycle completes
(i.e., SCIP bit is 0) after software sets the GO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset. When this bit is set and the SPI
SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block.
Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for
a new programmed access.
Hardware reset is initiated by one of the following resets:
Reserved
SPI Cycle In Progress (SCIP): — RO. Hardware sets this bit when software sets the
SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes
on the SPI interface. Hardware automatically sets and clears this bit so that software
can determine when read data is valid and/or when it is safe to begin programming the
next command. Software must only program the next command when this bit is 0.
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
non-ME systems.
ME enabled systems.
non-ME systems.
ME enabled systems.
00h
Description
Attribute:
Size:
RO, R/WC
8 bits
)
785