NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 279

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.32
7.1.33
Intel
®
ICH8 Family Datasheet
ILCL—Internal Link Capabilities List Register
Offset Address: 01A0–01A3h
Default Value:
LCAP—Link Capabilities Register
Offset Address: 01A4–01A7h
Default Value:
(Desktop
(Mobile
31:20
19:16
31:18
17:15
14:12
11:10
11:10
15:0
Only)
Only)
Bit
9:4
3:0
Bit
Next Capability Offset (NEXT) — RO. Indicates this is the last item in the list.
Capability Version (CV) — RO. Indicates the version of the capability structure.
Capability ID (CID) — RO. Indicates this is capability for DMI.
Reserved
L1 Exit Latency (EL1) — L1 not supported on DMI.
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to less
than 256 ns.
Reserved
Active State Link PM Support (APMS) — R/WO. Indicates that L0s is supported on
DMI.
Maximum Link Width (MLW) — Indicates the maximum link width is 4 ports.
Maximum Link Speed (MLS) — Indicates the link speed is 2.5 Gb/s.
00010006h
00012441h
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
32-bit
RO/ R/WO
32-bit
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