NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 673

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Intel
17.2.7
17.2.8
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
WAKEEN—Wake Enable Register
(Intel
Memory Address:HDBAR + 0Ch
Default Value:
STATESTS—State Change Status Register
(Intel
Memory Address:HDBAR + 0Eh
Default Value:
15:4
15:4
3:0
3:0
Bit
Bit
Reserved.
SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may
generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is
enabled to generate a wake.
Bit 0 is used for SDI[0]
Bit 1 is used for SDI[1]
Bit 2 is used for SDI[2]
Bit 3 is used for SDI[3]
NOTE: These bits are in the resume well and only cleared on a power on reset.
Reserved.
SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s)
received a state change event. The bits are cleared by writing 1’s to them.
Bit 0 = SDI[0]
Bit 1 = SDI[1]
Bit 2 = SDI[2]
Bit 3 = SDI[3]
NOTE: These bits are in the resume well and only cleared on a power on reset.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
0000h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
16 bits
R/WC
16 bits
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