NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 544
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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13.1.10
.
13.1.11
.
13.1.12
544
PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5)
Address Offset: 10h
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5)
Address Offset: 14h
Default Value:
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1)
Address Offset: 18h
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Secondary Controller’s Command
31:16
31:16
31:16
15:3
15:3
15:2
2:1
Bit
Bit
2:1
Bit
0
0
1
0
Block.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (4
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
00000001h
00000001h
00000001h
–
–
–
13h
17h
1Bh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F5)
R/W, RO
32 bits
R/W, RO
32 bits
R/W, RO
32 bits
Intel
®
ICH8 Family Datasheet
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