NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 788

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

20.3.17
Note:
788
OPMENU—Opcode Menu Configuration Register
(
Memory Address:GLBAR + 98h
Default Value:
Eight entries are available in this register to give GbE a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
It is recommended that GbE avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
This register is not writable when the SPI Configuration Lock-Down bit (GLBAR +
00h:15) is set.
63:56
55:48
47:40
39:32
31:24
23:16
GbE LAN Memory Mapped Configuration Registers
15:8
7:0
Bit
Allowable Opcode 7 — R/W. See the description for bits 7:0
Allowable Opcode 6 — R/W. See the description for bits 7:0
Allowable Opcode 5 — R/W. See the description for bits 7:0
Allowable Opcode 4 — R/W. See the description for bits 7:0
Allowable Opcode 3 — R/W. See the description for bits 7:0
Allowable Opcode 2 — R/W. See the description for bits 7:0
Allowable Opcode 1 — R/W. See the description for bits 7:0
Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use
when initiating SPI commands through the Control Register.
0000000000000000h
§ §
Description
Attribute:
Size:
Serial Peripheral Interface (SPI)
R/W
64 bits
)
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ICH8 Family Datasheet