NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 314

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

8.1.10
8.1.11
314
MBARA—Memory Base Address Register A
(Gigabit LAN—D25:F0)
Address Offset: 10h
Default Value:
The internal CSR registers and memories are accessed as direct memory mapped
offsets from the base address register. SW may only access whole DWord at a time.
MBARB—Memory Base Address Register B
(Gigabit LAN—D25:F0)
Address Offset: 14h
Default Value:
The internal registers that are used to access the LAN Space in the External FLASH
device. Accessed to these registers are direct memory mapped offsets from the base
address register. SW may only access a DWord at a time.
31:15
31:12
14:4
11:4
2:1
2:1
Bit
Bit
3
0
3
0
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
Memory Size (MSIZE) — R/W. Memory size is 32 KB.
Prefetchable Memory (PM) — RO. The Gb LAN controller does not implement
prefetchable memory.
Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.
Memory / IO Space (MIOS) — RO. Set to ‘0’ indicating a Memory Space BAR.
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
Memory Size (MSIZE) — R/W. Memory size is 4K Bytes.
Prefetchable Memory (PM) — RO. The Gb LAN controller does not implement
prefetchable memory.
Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.
Memory / IO Space (MIOS) — RO. Set to ‘0’ indicating a Memory Space BAR.
00000000h
00000001h
–
–
13h
17h
Description
Description
Attribute:
Size:
Attribute:
Size:
Gigabit LAN Configuration Registers
R/W, RO
32 bits
R/W, RO
32 bits
Intel
®
ICH8 Family Datasheet