NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 641
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
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SMBus Controller Registers (D31:F3)
16.2.18
Note:
16.2.19
Note:
Intel
®
ICH8 Family Datasheet
NOTIFY_DLOW—Notify Data Low Byte Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 16h
Default Value:
This register is in the resume well and is reset by RSMRST#.
NOTIFY_DHIGH—Notify Data High Byte Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 17h
Default Value:
This register is in the resume well and is reset by RSMRST#.
7:0
7:0
Bit
Bit
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)
is set to 1.
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)
is set to 1.
00h
00h
Description
§ §
Description
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
641
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