NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 422

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

9.9.9
9.9.10
9.9.11
422
TCO_WDCNT—TCO Watchdog Control Register
Offset Address: TCOBASE + 0Eh
Default Value:
Power Well:
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: TCOBASE + 10h
Default Value:
Power Well:
TCO_TMR—TCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
15:10
7:2
9:0
7:0
Bit
Bit
Bit
1
0
Reserved
IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as
received by the ICH8’s SERIRQ logic. This bit must be a 1 (default) if the ICH8 is
expected to receive IRQ12 assertions from a SERIRQ device.
IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as
received by the ICH8’s SERIRQ logic. This bit must be a 1 (default) if the ICH8 is
expected to receive IRQ1 assertions from a SERIRQ device.
Reserved
TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the
TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not
be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows
timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of ±
1 tick (0.6s).
The TCO Timer will only count down in the S0 state.
The BIOS or system management software can write into this register to indicate more
details on the boot progress. The register will reset to 00h based on a RSMRST# (but
not PLTRST#). The external microcontroller can read this register to monitor boot
progress.
00h
Resume
03h
Core
TCOBASE +12h
0004h
No
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bits
R/W
8 bits
R/W
16-bit
Core
Intel
®
ICH8 Family Datasheet