EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 754
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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3–8
Table 3–4. Configuration for Example 2
Stratix IV Device Handbook Volume 2
Instance Name
User-Created
inst0
inst1
inst2
1
Figure 3–2
channel instances.
Figure 3–2. Combined Instances after Compilation for Example 1
Example 2
Consider the example design shown in
the same serial data rate but with different CMU PLL data rates, the Quartus II
software creates a separate CMU PLL for the two instances.
Even though the effective data rate of inst1 is 2.5 Gbps (5 Gbps/2 = 2.5 Gbps), the
same as inst0, when you compile the design, the Quartus II software requires two
CMU PLLs to provide clocks for the transmitter side of the two instances because
their base data rates are different. In this example, you have the third instance, inst2,
that requires a third CMU PLL. Therefore, the Quartus II software cannot combine the
above three instances within the same transceiver block.
Number of Channels
1
1
1
show the scenario after the Quartus II software combines the transceiver
ALTGX MegaWizard Plug-In Manager Settings
Chapter 3: Configuring Multiple Protocols and Data Rates in a Transceiver Block
Configuration
Receiver and
Receiver and
Receiver and
Transmitter
Transmitter
Transmitter
Effective Data Rate: 1.0625 Gbps
Inst 0
Effective Data Rate: 4.25 Gbps
Inst 1
Effective Data Rate: 2.125 Gbps
Inst 2
Inst 3
Effective Data Rate: 4.25 Gbps
TX Loc Div: /1
TX Loc Div: /1
TX Loc Div: /2
TX Loc Div: /4
Transceiver Block
Table
Base Data Rate:
4.25 Gbps
CMU PLL
3–4. When you have two instances with
Data Rate
Effective
2.5 Gbps
2.5 Gbps
1 Gbps
© November 2009 Altera Corporation
Base Data Rate
2.5 Gbps
5 Gbps
1 Gbps
Sharing CMU PLLs
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