EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 736
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
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2–72
Stratix IV Device Handbook Volume 2
To use this feature, you must create an ALTGX instance with a single channel in
Transmitter Only mode that uses the required CMU PLL or ATX PLL. Follow these
steps to create the ALTGX instance:
1. Choose Basic (PMA Direct) ×N mode as the protocol.
2. Select Transmitter Only operation mode.
3. Select the input clock frequency.
4. Select the appropriate values of data rate and channel width based on the desired
Equation 2–1.
5. You can select the PLL bandwidth by choosing Tx PLL bandwidth mode.
6. You can instantiate the pll_locked port to indicate the PLL lock status.
7. You can instantiate pll_powerdown or gxb_powerdown to enable the PLL PFD
8. Use tx_clkout of the ALTGX instance as the clock source for clocking user logic
output clock frequency. To generate a 250 MHz clock using an input clock
frequency of 50 MHz, select a channel width of 10 and a data rate of 2500 Mbps
(Equation
power down control.
in the FPGA fabric.
2–1).
f
out
=
Using the CMU/ATX PLL for Clocking User Logic in the FPGA Fabric
channel width
data rate
Chapter 2: Stratix IV Transceiver Clocking
© March 2010 Altera Corporation
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