EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 726

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–62
Figure 2–33. FPGA Fabric-Receiver Interface Clocking for Example 6
Note to
(1) The green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock.
Stratix IV Device Handbook Volume 2
Figure
and Status
and Status
and Status
Channel 3
and Status
Channel 1
Channel 0
Channel 2
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
2–33:
FPGA
Fabric
rx_coreclk[0]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[3]
Figure 2–33
tx_clkout[2]
tx_clkout[0]
Reference
shows the FPGA fabric-Receiver interface clocking for Example 6.
Reference
Clock
Clock
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
CMU1
CMU0
rdclk
rdclk
RX Phase
RX Phase
PLL
PLL
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
/2
/2
/2
/2
(Note 1)
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
CMU1 Channel
CMU0 Channel
Chapter 2: Stratix IV Transceiver Clocking
FPGA Fabric-Transceiver Interface Clocking
© March 2010 Altera Corporation
Channel 1
Channel 3
Channel 2
Channel 0
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Transmitter Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Divider Block
Divider Block
Local Clock
Divider Block
Local Clock
High-Speed Serial Clock
Divider Block
Local Clock
Local Clock