EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 652
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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1–214
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 5 of 8)
Stratix IV Device Handbook Volume 2
rx_errdetect
rx_disperr
rx_runningdisp
Port Name
Output
Output
Output
Output
Input/
tx_clkout for
tx_clkout for
tx_clkout for
tx_clkout or
tx_clkout or
tx_clkout or
Synchronous to
coreclkout.
Synchronous to
coreclkout.
Synchronous to
coreclkout.
coreclkout
coreclkout
coreclkout
Clock Domain
non-bonded
non-bonded
non-bonded
for bonded
for bonded
for bonded
modes.
modes.
modes.
modes.
modes.
modes.
8B/10B code group violation or disparity error
indicator.
■
■
■
8B/10B disparity error indicator port.
■
■
■
8B/10B running disparity indicator.
■
■
■
■
Available in configurations with 8B/10B
decoder.
A high level—a code group violation or
disparity error was detected on the
associated received code group. Use with
the rx_disperr signal to differentiate
between a code group violation and/or a
disparity error as follows:
Channel Width:
8—rx_errdetect = 1
16—rx_errdetect = 2
32—rx_errdetect = 4
Available in configurations with 8B/10B
decoder.
A high level—a disparity error was detected
on the associated received code group.
Channel Width:
8—rx_disperr = 1
16—rx_disperr = 2
32—rx_disperr = 4
Available in configurations with the 8B/10B
decoder.
A high level—the data on the rx_dataout
port was received with a negative running
disparity.
A low level—the data on the rx_dataout
port was received with a positive running
disparity.
Channel Width:
8—rx_runningdisp = 1
16—rx_runningdisp = 2
32—rx_runningdisp = 4
[rx_errdetect: rx_disperr]
2’b00—no error
2’b10—code group violation
2’b11—disparity error or both
Description
Chapter 1: Stratix IV Transceiver Architecture
© March 2010 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Scope
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