EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 643
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Stratix IV Transceiver Architecture
Built-In Self Test Modes
Figure 1–170. BIST PRBS, High Frequency, and Low Frequency Pattern Datapath
© March 2010 Altera Corporation
FPGA
Fabric
Compen-
Phase
Compen-
sation
FIFO
Phase
sation
TX
FIFO
RX
Three types of pattern generators and verifiers are available:
■
■
■
Different PRBS patterns are available as a subprotocol under Basic functional mode
for single-width and double-width mode, as shown in the following sections.
You can enable the serial loopback option in Basic PRBS mode to loop the generated
pattern to the receiver channel. This creates a rx_seriallpbken port that you can
use to dynamically control the serial loopback. The 8B/10B encoder/decoder blocks
are bypassed in Basic PRBS mode.
Figure 1–170
sent to the transmitter serializer. The verifier checks the data from the word aligner.
Ordering
BIST incremental data generator and verifier—This is only available in parallel
loopback mode. For more information, refer to
High frequency and low frequency pattern generator—The high frequency
patterns generate alternate ones and zeros and the low frequency patterns
generate five ones and five zeroes in single-width mode and ten ones and ten
zeroes in double-width mode. These patterns do not have a corresponding verifier.
You can enable the serial loopback option to dynamically loop the generated
pattern to the receiver channel using the rx_seriallpbken port. Therefore, the
8B/10B encoder/decoder blocks are bypassed in the Basic PRBS mode.
Pseudo Random Binary Sequence (PRBS) generator and verifier—The PRBS
generator and verifier interface with the serializer and deserializer in the PMA
blocks. The advantage of using a PRBS data stream is that the randomness yields
an environment that stresses the transmission medium. In the data stream, you
can observe both random jitter and deterministic jitter using a time interval
analyzer, bit error rate tester, or oscilloscope. The PRBS repeats after completing an
iteration. The number of bits the PRBSx pattern sends before repeating the pattern
is (2
Byte
Serializer
Byte
^x -1
) bits.
serializer
shows the datapath for the PRBS patterns. The generated PRBS pattern is
Byte
De-
Encoder
8B/10B
BIST PRBS, High-Freq,
Low-Freg pattern
Receiver Channel PCS
Decoder
8B/10B
generator
Match
FIFO
Rate
Transmitter Channel PCS
BIST PRBS verifier
Deskew
FIFO
“Serial Loopback” on page
Aligner
Word
serializer
Receiver Channel
Serializer
Transmitter Channel PMA
Stratix IV Device Handbook Volume 2
De-
PMA
Receiver
CDR
can be dynamically enabled
Serial loop back
1–188.
1–205
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