EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 570

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–132
Figure 1–107. Compliance Pattern Transmission Support, 8-Bit Channel Width Configurations
Stratix IV Device Handbook Volume 2
tx_forcedispcompliance
tx_datain[7:0]
tx_ctrldetect
Compliance Pattern Transmission Support
The LTSSM state machine can enter the polling.compliance substate where the
transmitter is required to transmit a compliance pattern as specified in the PCI
Express (PIPE) Base Specification 2.0. The polling.compliance substate is intended to
assess if the transmitter is electrically compliant with the PCI Express (PIPE) voltage
and timing specifications.
The compliance pattern is a repeating sequence of the following four code groups:
■
■
■
■
The PCI Express (PIPE) protocol requires the first /K28.5/ code group of the
compliance pattern to be encoded with negative current disparity. To satisfy this
requirement, the PCI Express (PIPE) interface block provides the input signal
tx_forcedispcompliance. A high level on tx_forcedispcompliance forces
the associated parallel transmitter data on the tx_datain port to transmit with
negative current running disparity.
■
■
Figure 1–107
tx_forcedispcompliance signal while transmitting the compliance pattern in
8-bit and 16-bit channel width configurations, respectively.
/K28.5/
/D21.5/
/K28.5/
/D10.2/
For 8-bit transceiver channel width configurations, you must drive
tx_forcedispcompliance high in the same parallel clock cycle as the first
/K28.5/ of the compliance pattern on the tx_datain port.
For 16-bit transceiver channel width configurations, you must drive only the LSB
of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as
/K28.5/D21.5/ of the compliance pattern on the tx_datain port.
K28.5
BC
and
Figure 1–108
D21.5
B5
K28.5
BC
show the required level on the
D10.2
4A
K28.5
BC
Chapter 1: Stratix IV Transceiver Architecture
D21.5
B5
K28.5
BC
© March 2010 Altera Corporation
Transceiver Block Architecture
D10.2
4A