EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 208
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #6
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6–34
Stratix IV Device Handbook Volume 1
1
Sharing an OCT Calibration Block on Multiple I/O Banks
An OCT calibration block has the same V
OCT R
standards, up to the number of available OCT calibration blocks. You can configure
the I/O banks to receive calibration codes from any OCT calibration block with the
same V
even if that particular I/O bank has an OCT calibration block.
For example,
If a group of I/O banks has the same V
block to calibrate the group of I/O banks placed around the periphery. Because 3B,
4C, 6C, and 7B have the same V
(3B, 4C, 6C, and 7B) with the OCT calibration block (CB7) located in bank 7A. You can
enable this by serially shifting out OCT R
block located in bank 7A to the I/O banks located around the periphery.
I/O banks that do not contain calibration blocks share calibration blocks with I/O
banks that do contain calibration blocks.
Figure 6–23
chip packages. It is a graphical representation only. This figure does not show
transceiver banks and transceiver calibration blocks.
Figure 6–23. Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
S
CCIO
calibration is supported on all I/O banks with different V
. All I/O banks with the same V
is a top view of the silicon die that corresponds to a reverse view for flip
Figure 6–23
Stratix IV
shows a group of I/O banks that has the same V
CCIO
as bank 7A, you can calibrate all four I/O banks
CCIO
CCIO
S
calibration codes from the OCT calibration
CCIO
voltage, you can use one OCT calibration
Bank 6A
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
as the I/O bank that contains the block.
can share one OCT calibration block,
Chapter 6: I/O Features in Stratix IV Devices
© March 2010 Altera Corporation
I/O bank with the same V
I/O bank with different V
CCIO
voltage
CCIO
OCT Calibration
voltage.
CCIO
CCIO
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