EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 771
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 3: Configuring Multiple Protocols and Data Rates in a Transceiver Block
Combining Transceiver Channels with Basic (PMA Direct) Configuration
Combining Multiple Channels Configured in Basic (PMA Direct) ×1 Configurations
© November 2009
Altera Corporation
When you configure a transceiver channel in Basic (PMA Direct) ×1 configuration, the
Quartus II software requires one of the two CMU PLLs within the same transceiver
block to provide high-speed clocks to the transmitter side of the channel (you cannot
use the ATX PLL). Therefore, within a transceiver block, you can only combine a
maximum of five transceiver channels (using both Transmitter and Receiver)
configured in Basic (PMA Direct) ×1 mode (one CMU channel to perform the clock
multiplication unit functionality).
You can configure the transmitter side of the CMU channel that uses its CMU PLL for
clock generation in Basic (PMA Direct) x1 in single-width or double-width
configuration, as shown in
There are multiple ways you can combine channels in Basic (PMA Direct) ×1 mode
within the same transceiver block:
■
■
■
■
Multiple Basic (PMA Direct) ×1 Configuration Instances with One Channel per
Instance
If you create multiple instances of Basic (PMA Direct) ×1 with one channel per
instance, you can combine them within the same transceiver block. To achieve this
combination, refer to the requirements specified in
CMU PLL” on page 3–5
page
high-speed clock for the transmitter side of the channels. Therefore, at least one CMU
channel (that contains the CMU PLL) within the transceiver block must be available to
generate high-speed serial and low-speed parallel clocks for the channels configured
in this mode. You can also place the individual instances in this configuration in
separate transceiver blocks. For this placement, the Quartus II software enables one
CMU PLL per instance.
One Instance in Basic (PMA Direct) ×1 Configuration with Multiple Transceiver
Channels
In this case, if the number of channels selected in the instance is less than six, the
Quartus II software, by default, combines these channels within the same transceiver
block and uses one CMU PLL to provides high-speed clocks. If the number of
channels is six or more, the Quartus II software requires two transceiver blocks and
two CMU PLLs, one from each transceiver block.
The following two examples show the combinations of channels under two different
conditions.
“Multiple Basic (PMA Direct) ×1 Configuration Instances with One Channel per
Instance” on page 3–25
“One Instance in Basic (PMA Direct) ×1 Configuration with Multiple Transceiver
Channels” on page 3–25
“Combining Multiple Instances of TX Only and RX Only Configurations in Basic
(PMA Direct) ×1 Mode” on page 3–28
“Combining Channels Configured in Basic (PMA Direct) ×1 with Non-Basic (PMA
Direct) Modes” on page 3–28
3–3. Note that one CMU PLL within the transceiver block must provide a
and
Figure 3–17 on page
“General Requirements to Combine Channels” on
3–31.
“Multiple Channels Sharing a
Stratix IV Device Handbook Volume 2
3–25
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