EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 624

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–186
Figure 1–150. Stratix IV GX and GT Transceiver Configured in Basic (PMA Direct) Mode
Note to
(1) The grayed out blocks shown in
Stratix IV Device Handbook Volume 2
as transceiver channels in PMA direct mode only.
Fabric
FPGA
Figure
1–150:
1
Figure 1–150
(PMA Direct) functional mode. The grayed out blocks indicate areas that are not
active in this mode.
The grayed out blocks shown in
Therefore, the CMU channels can be configured to operate as transceiver channels in
PMA Direct mode only.
In Basic (PMA Direct) Mode, you can configure the transceiver channel in two main
configurations:
■
■
You can configure the transceiver in Basic (PMA Direct) ×1/ ×N mode by setting the
appropriate sub-protocol in the Which sub protocol will you be using? field. You can
select single-width or double-width by selecting Single/Double in the What is the
deserializer block width? field in the ALTGX MegaWizard Plug-In Manager.
In single-width mode, the PMA-PLD interface is 8 bit/10 bit wide; whereas in
double-width mode, the PMA-PLD interface is 16 bit/20 bit wide.
Basic (PMA Direct) ×1 configuration
Basic (PMA Direct) ×N configuration
Figure 1–150
Compensation
shows the Stratix IV GX and GT transceiver configured in Basic
wrclk
TX Phase
FIFO
are not available in the CMU channels. Therefore, the CMU channels can be configured to operate
rdclk
wrclk
Byte Serializer
Receiver Channel PCS
Transmitter Channel PCS
Figure 1–150
rdclk
are not available in the CMU channels.
8B/10B Encoder
Chapter 1: Stratix IV Transceiver Architecture
© March 2010 Altera Corporation
Transceiver Block Architecture
Transmitter Channel
Receiver Channel
PMA
PMA