EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 480
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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1–42
Table 1–20. Settings for a Stratix II GX to Stratix IV GX DC-Coupled Link
Stratix IV Device Handbook Volume 2
600-6375 Mbps
Note to
(1) V
Data Rate
from 600 Mbps to 6375 Mbps.
CCH
Table
= 1.5 V with TX V
1–20:
Transmitter (Stratix II GX) Settings
(1.5 V PCML)
V
CM
Figure 1–35
(PCML) coupled link.
Figure 1–35. Stratix II GX Transmitter (PCML) to Stratix IV GX Receiver (PCML)
Note to
(1) R
Table 1–20
Stratix IV GX DC-coupled link.
1.5 V
CCH
= 0.7 V can support data rates from 600 Mbps to 3125 Mbps. V
(1)
S
is the parasitic resistance present in the on-chip RX termination and biasing circuitry.
Figure
shows the allowed transmitter and receiver settings in a Stratix II GX to
Stratix II GX
Transmitter
50/60/75-
TX Termination
1–35:
0.6 V/0.7 V
TX V
shows the Stratix II GX transmitter (PCML) to Stratix IV GX receiver
V
CCH
CM
= 1.2 V/1.5 V
Ω
(1)
TX
V
CM
100/120/150 Ω
Termination
Differential
50/60/75-
TX Termination
0.6 V/0.7 V
Physical Medium
Physical Medium
Ω
600-6375 Mbps
42.5/50/60/75-
RX Termination
Data Rate
CCH
= 1.5 V with TX V
Receiver (Stratix IV GX) Settings
Chapter 1: Stratix IV Transceiver Architecture
Ω
RX
V
CM
R
s
RX V
0.82 V
0.82 V
© March 2010 Altera Corporation
42.5/50/60/75-
RX Termination
CM
(1)
= 0.6 V can support data rates
CM
Transceiver Block Architecture
Stratix IV GX
Receiver
Ω
100/120/150 Ω
Termination
Differential
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