EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 583

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Figure 1–114. Dynamic Switch Signaling in PCI Express (PIPE) ×8 Mode
© March 2010 Altera Corporation
Fabric
FPGA
Interface
Interface
rateswitch
PIPE
PIPE
controller automatically disables and resets the phase compensation FIFO pointers of
all bonded channels during clock switch. When the PCI Express (PIPE) clock switch
circuitry in the local clock divider indicates successful clock switch completion, the
PCI Express (PIPE) rateswitch controller releases the phase compensation FIFO
pointer resets.
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCI
Express (PIPE) ×8 Mode
Figure 1–114
×8 mode configured at Gen2 (5 Gbps) data rate.
reset_int
reset_int
reset_int
reset_int
Compensation
Compensation
Compensation
Compensation
Transceiver
Transceiver
Transmitter
Transmitter
Controller
Receiver
Receiver
Express
Phase
Phase
Phase
Phase
Switch
PCS
FIFO
FIFO
PCS
FIFO
FIFO
Rate
PCI
CCU
shows the PCI Express (PIPE) rateswitch circuitry in PCI Express (PIPE)
rx_locktorefclk
rx_freqlocked
rx_locktodata
signal detect
rx_datain
rx_cruclk
rx_datain
rx_cruclk
CMU0
CMU1
PLL
PLL
rx_locktorefclk
rx_freqlocked
rx_locktodata
signal detect
/1, /2, /4
/1, /2, /4
pcie_gen2switch_done
pcie_gen2switch
/2
/2
Frequency
Frequency
Controller
Controller
LTR/LTD
Detector
Detector
LTR/LTD
Detector
Detector
pcie_gen2switch
Phase
Phase
Phase
Phase
(PD)
(PD)
(PD)
(PD)
Clock and Data Recovery (CDR) Unit
Clock and Data Recovery (CDR) Unit
/1, /2, /4
rateswitch_asn
CMU0 Clock Divider
CMU1 Clock Divider
/1, /2, /4
pcie_gen2switch
Clock Switch
PCI Express
rateswitch_asn
Circuitry
Loop Filter
Loop Filter
Pump +
Pump +
Charge
Charge
/4, /5, /8, /10
1
0
1
0
V
V
/M
/M
CO
CO
CMU0_Channel
CMU1_Channel
/2
/2
/4, /5, /8, /10
Stratix IV Device Handbook Volume 2
PCI Express Clock Switch Circuitry
/L
/L
Master Transceiver Block
Slave Transceiver Block
in the Master and Slave
the Master and Slave
Bonded Channels in
Low-Speed Parallel
Transceiver Blocks
Transceiver Blocks
Clock to the Eight
High-Speed Serial
Bonded Channels
Clock to the Eight
Recovered
Recovered
Recovered
Recovered
Parallel
Parallel
Serial
Clock
Clock
Serial
Clock
Clock
1–145