EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 531
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
© March 2010 Altera Corporation
1
Byte Ordering Block in Double-Width Modes
Table 1–35
Table 1–35. Double Width Functional Modes for the Byte Ordering Block
For more information about configurations that allow the byte ordering block in the
receiver datapath, refer to
In Basic double-width modes, you can program a custom byte ordering pattern and
byte ordering PAD pattern in the ALTGX MegaWizard Plug-In Manager.
shows the byte ordering pattern length allowed in Basic double-width mode.
Table 1–36. Byte Ordering Pattern Length in Basic Double-Width Mode
Basic double-width mode with:
Basic double-width mode with:
Basic double-width mode with:
Basic double-width mode with:
■
■
■
Basic double-width mode with:
■
■
■
Basic double-width mode with:
■
■
■
Note to
(1) The 18-bit byte ordering pattern D[17:0] consists of MSByte D[17:9] and LSByte D[8:0]; D[17]
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
40-bit FPGA fabric-transceiver interface
No 8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
corresponds to rx_ctrldetect[1] and D[16:9] corresponds to rx_dataout[15:8]. Similarly, D[9]
corresponds to rx_ctrldetect[0] and D[7:0] corresponds to rx_dataout[7:0].
Table
Functional Modes
lists the double-width byte ordering block functional modes.
1–36:
Functional Mode
“Basic Double-Width Mode Configurations” on page
■
■
■
■
■
■
■
■
■
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
40-bit FPGA fabric-transceiver interface
No 8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
18 bits, 9 bits
Pattern Length
20 bits, 10 bits
Byte Ordering
16 bits, 8 bits
Descriptions
Stratix IV Device Handbook Volume 2
(1)
Byte Ordering PAD
Pattern Length
10 bits
Table 1–36
8 bits
9 bits
1–114.
1–93
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