EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 478
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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1–40
Stratix IV Device Handbook Volume 2
DC-Coupled Links
In a DC-coupled link, the transmitter DC V
Link V
receiver termination and biasing circuitry must ensure compatibility between the
transmitter and the receiver V
Figure 1–33. DC-Coupled Link
Note to
(1) The receiver termination and biasing can be on-chip or off-chip.
You might choose to use the DC-coupled high-speed link for these functional modes
only:
■
■
The following sections describe DC-coupling requirements for a high-speed link with
a Stratix IV GX device used as the transmitter, receiver, or both. Specifically, the
following link configurations are described:
■
■
■
■
Basic single- and double-width
(OIF) CEI PHY interface
Stratix IV GX Transmitter (PCML) to Stratix IV GX Receiver (PCML)
Stratix II GX Transmitter (PCML) to Stratix IV GX Receiver (PCML)
Stratix IV GX Transmitter (PCML) to Stratix II GX Receiver (PCML)
LVDS Transmitter to Stratix IV GX Receiver (PCML)
Figure
CM
depends on the transmitter V
Transmitter
1–33:
TX Termination
TX
V
CM
CM
.
Figure 1–33
Physical Medium
Physical Medium
CM
and the receiver V
CM
shows a DC-coupled link.
is seen unblocked at the receiver buffer.
Chapter 1: Stratix IV Transceiver Architecture
RX
V
CM
CM
© March 2010 Altera Corporation
. The on-chip or off-chip
RX Termination
Transceiver Block Architecture
Receiver
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