EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 457
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Figure 1–12. 8B/10B Encoder in Single-Width Mode
© March 2010 Altera Corporation
control_code
Byte Serializer
tx_forcedisp
Single Width
datain[7:0]
tx_dispval
From the
8B/10B Encoder
The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control
identifier. The 8B/10B encoder operates in two modes: single-width and
double-width.
double-width mode.
Single-Width Mode
The left side of
mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control
word or data word) with proper disparity. If the control_code input is high, the
8B/10B encoder translates the input data[7:0] to a 10-bit control word. If the
control_code input is low, the 8B/10B encoder translates the input data[7:0] to
a 10-bit data word.
You can use the tx_forcedisp and tx_dispval ports to control the running
disparity of the generated output data. For more information, refer to
Running Disparity” on page
8B/10B Encoder
Figure 1–12
Figure 1–12
To the Serializer
dataout[9:0]
shows the 8B/10B encoder in single-width and
shows the 8B/10B encoder in single-width mode. In this
1–23.
Double Width
control_code[1]
control_code[0]
tx_forcedisp[0]
tx_forcedisp[1]
Byte Serializer
tx_dispval[0]
datain[15:8]
tx_dispval[1]
From the
datain[7:0]
8B/10B Encoder
MSB Encoding
LSB Encoding
Stratix IV Device Handbook Volume 2
To the Serializer
dataout[19:10]
dataout[9:0]
“Controlling
1–19
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