EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 41

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Logic Array Blocks
© November 2009
SIV51002-3.0
Altera Corporation
This chapter describes the features of the LABs in the Stratix IV core fabric. LABs are
made up of ALMs you can configure to implement logic functions, arithmetic
functions, and register functions.
Logic array blocks (LABs) and adaptive logic modules (ALMs) are the basic building
blocks of the Stratix
arithmetic functions, and register functions. The ALM provides advanced features
with efficient logic utilization and is completely backward-compatible.
This chapter contains the following sections:
■
■
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
control signals, local interconnect, and register chain connection lines. The local
interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect allows the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus
the LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
Stratix IV LAB structure and the LAB interconnects.
“Logic Array Blocks” on page 2–1
“Adaptive Logic Modules” on page 2–5
2. Logic Array Blocks and Adaptive Logic
®
IV device. You can use these to configure logic functions,
Modules in Stratix IV Devices
®
II Compiler places associated logic in
Stratix IV Device Handbook Volume 1
Figure 2–1
shows the