EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 458
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–20
Figure 1–14. Control Word and Data Word Transmission
Stratix IV Device Handbook Volume 2
tx_datain[7:0]
tx_ctrlenable
code group
clock
Figure 1–13
Figure 1–13. 8B/10B Conversion Format
Control Code Encoding
The ALTGX MegaWizard Plug-In Manager provides the tx_ctrlenable port to
indicate whether the 8-bit data at the tx_datain port should be encoded as a control
word (Kx.y). When tx_ctrlenable is low, the 8B/10B encoder block encodes the
byte at the tx_datain port (the user-input port) as data (Dx.y). When
tx_ctrlenable is high, the 8B/10B encoder encodes the input data as a Kx.y code
group. The waveform in
word (K28.5). The rest of the tx_datain bytes are encoded as a data word (Dx.y).
The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters
for which tx_ctrlenable should be asserted. If you assert tx_ctrlenable for
any other set of bytes, the 8B/10B encoder might encode the output 10-bit code as an
invalid code (it does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y
code, depending on the value entered. It is possible for a downstream 8B/10B decoder
to decode an invalid control word into a valid Dx.y code without asserting code error
flags.
D3.4
83
shows the conversion format. The LSB is transmitted first.
D24.3
78
H G F E D C B A
7
MSB
j
9
Figure 1–14
6
BC
D28.5
h
8
5
g
7
4
8B/10B Conversion
K28.5
f
6
BC
3
i
5
shows the second 0 × BC encoded as a control
2
e d c b a
4
1
D15.0
0F
3
0
2
1
D0.0
control_code
00
Chapter 1: Stratix IV Transceiver Architecture
LSB
0
D31.5
BF
© March 2010 Altera Corporation
Transceiver Block Architecture
D28.1
3C
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