EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 455

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
© March 2010 Altera Corporation
Single-Width Mode
Figure 1–10
width, refer to
Figure 1–10. Byte Serializer Datapath in Single-Width Mode
Notes to
(1) For the datain[] and dataout[] port widths, refer to
(2) The datain signal is the input from the FPGA fabric that has already passed through the TX phase compensation
The byte serializer forwards the LSByte first, followed by the MSByte. The input data
width to the byte serializer depends on the channel width option that you selected in
the ALTGX MegaWizard Plug-In Manager. For example, in single-width mode,
assuming a channel width of 20, the byte serializer sends out the least significant
word datain[9:0] of the parallel data from the FPGA fabric, followed by
datain[19:10].
serializer in single-width mode.
Table 1–9. Input and Output Data Width of the Byte Serializer in Single-Width Mode
Single-width mode
FIFO.
Deserialization Width
Figure
shows the byte serializer datapath in single-width mode. For data port
1–10:
Table
Table 1–9
1–9.
datain[]
lists the input and output data widths of the byte
Input Data Width to the Byte
Byte Serializer
Serializer
/2
16
20
Table
dataout[]
1–9.
Low-Speed Parallel
(Note
Clock
1),
Stratix IV Device Handbook Volume 2
(2)
Output Data Width from the
Byte Serializer
10
8
1–17