EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 990

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–40
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 1 of 4)
Stratix IV Device Handbook Volume 3
Use manual word alignment
mode.
When should the word aligner
realign?
Use manual bitslipping mode.
Use the Automatic
synchronization state machine
mode.
Number of continuous valid
code groups received to
reduce the error count by 1.
ALTGX Setting
1
Table 1–12
MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
The word aligner and rate matcher operations and patterns are pre-configured for PCI
Express (PIPE), GIGE, and XAUI modes, and cannot be altered.
Enabling this option sets the word aligner in Manual
Alignment mode. In Manual Alignment mode, the
word aligner operation is controlled by the input signal
rx_enapatternalign.
Two options are available in manual mode:
■
■
This option sets the word aligner in Bit-Slip mode.
Enabling this option creates an input signal
rx_bitslip to control the word aligner. At every
rising edge of the rx_bitslip signal, the bit slip
circuitry slips one bit into the received data stream,
effectively shifting the word boundary by one bit.
SDI
Because word alignment and framing occur after
de-scrambling, the word aligner in the receiver data
path is not useful in SDI systems. Altera recommends
driving the ALTGX rx_bitslip signal low to
prevent the word aligner from inserting bits in the
received data stream.
This option sets the word aligner in Automatic
Synchronization State Machine mode. This mode is
available only in Single-width mode for 8B/10B
encoded data:
■
or
■
Use this option in Automatic Synchronization State
Machine mode to indicate the number of continuous
valid code groups that it must receive between
erroneous code groups to reduce the error count by
one. The rx_syncstatus stays high as long as the
error count is less than the programmed error count.
Realign continuously while the
rx_enapatternalign signal is high.
Realign at the rising edge of the
rx_enapatternalign signal.
10-bit PCS-PMA Interface where the 8B/10B
encoder is enabled
10-bit PCS-PMA Interface where the 8B/10B is
disabled but the data is already 8B/10B encoded
describes the available options on the Word Aligner screen of the
Description
Chapter 1: ALTGX Transceiver Setup Guide
“Manual Alignment Mode Word
Aligner with 8-bit PMA-PCS
Interface Modes” and “Manual
Alignment Mode Word Aligner
with 10-bit PMA-PCS Interface
Modes” sections in the
Transceiver Architecture
“Manual Alignment Mode Word
Aligner with 8-bit PMA-PCS
Interface Modes” and “Manual
Alignment Mode Word Aligner
with 10-bit PMA-PCS Interface
Modes” sections in the
Transceiver Architecture
“Word Aligner” section in the
Stratix IV Transceiver Architecture
chapter.
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the
Transceiver Architecture
“Automatic Synchronization State
Machine Mode Word Aligner with
10-bit PMA-PCS Interface Mode”
section in the
Transceiver Architecture
© November 2009 Altera Corporation
Reference
Stratix IV
Stratix IV
Protocol Settings
Stratix IV
Stratix IV
chapter.
chapter.
chapter.
chapter.