EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 132

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–14
Stratix IV Device Handbook Volume 1
Figure 5–11
You can select the clock source for the GCLK select block either statically or
dynamically. You can statically select the clock source using a setting in the Quartus II
software or you can dynamically select the clock source using internal logic to drive
the multiplexer-select inputs. When selecting the clock source dynamically, you can
select either PLL outputs (such as C0 or C1) or a combination of clock pins or PLL
outputs.
Figure 5–11. Stratix IV GCLK Control Block
Notes to
(1) When the device is operating in user mode, you can dynamically control the clock select signals through internal
(2) When the device is operation in user mode, you can only set the clock select signals through a configuration file
The mapping between the input clock pins, PLL counter outputs, and clock control
block inputs is as follows:
■
■
■
The corner PLLs (L1, L4, R1, and R4) and the corresponding clock input pins
(PLL_L1_CLK and so forth) do not support dynamic selection for the GCLK network.
The clock source selection for the GCLK and RCLK networks from the corner PLLs
(L1, L4, R1, and R4) and the corresponding clock input pins (PLL_L1_CLK and so
forth) is controlled statically using configuration bit settings in the configuration file
(.sof or .pof) generated by the Quartus II software.
inclk[0] and inclk[1]—can be fed by any of the four dedicated clock pins on
the same side of the Stratix IV device
inclk[2]—can be fed by PLL counters C0 and C2 from the two center PLLs on
the same side of the Stratix IV device
inclk[3]—can be fed by PLL counters C1 and C3 from the two center PLLs on
the same side of the Stratix IV device
logic.
(SRAM object file [.sof] or programmer object file [.pof]) and cannot be dynamically controlled.
Figure
and
5–11:
Figure 5–12
CLKSELECT[1..0]
PLL Counter
This multiplexer
supports user-controllable
dynamic switching
Outputs
(1)
show the GCLK and RCLK select blocks, respectively.
2
2
CLKp
Pins
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
2
Enable/
Disable
GCLK
CLKn
Pin
Static Clock
Select (2)
Internal
Internal
Logic
Logic
Clock Networks in Stratix IV Devices
© March 2010 Altera Corporation