EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 253
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–21. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry
Notes to
(1) For possible reference input clock pins for each DLL, refer to
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
© March 2010 Altera Corporation
Figure
DQS/CQ
DQS/CQ
Pin
Pin
7–21:
CQn
CQn
Pin
Pin
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be
updated concurrently at every DQS/CQ or CQn pin.
Δt
Δt
Δt
Δt
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Clock
DQS
IOE
IOE
DQS
Clock
IOE
IOE
DLL
to
DLL
to
to
to
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
to IOE
CQn
Pin
Δt
“DLL” on page
DQS Logic
Blocks
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
7–32.
(Note
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
1),
to IOE
CQn
Pin
Δt
(2)
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Clock
Clock
DLL
DLL
DQS
DQS
IOE
IOE
IOE
IOE
to
to
to
to
Stratix IV Device Handbook Volume 1
DQS Logic
Blocks
Δt
Δt
Δt
Δt
CQn
DQS/CQ
CQn
DQS/CQ
Pin
Pin
Pin
Pin
7–31
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