EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 396
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10–64
Stratix IV Design Security Solution
Stratix IV Device Handbook Volume 1
f
f
1
1
After power-up, you must wait 300 ms (PORSEL = 0) or 12 ms (PORSEL = 1) before
beginning key programming to ensure that V
For more information about how to calculate the key retention time of the battery
used for volatile key storage, refer to the
For more information about battery specifications, refer to the
Characteristics
For more information about the V
Stratix IV GX Device Family Pin Connection
Stratix IV devices are SRAM-based devices. To provide design security, Stratix IV
devices require a 256-bit security key for configuration bitstream encryption.
You can carry out secure configuration in the following steps, as shown in
Figure
1. Program the security key into the Stratix IV device.
2. Program the user-defined 256-bit AES keys to the Stratix IV device through the
3. Encrypt the configuration file and store it in the external memory.
4. Encrypt the configuration file with the same 256-bit keys used to program the
5. Configure the Stratix IV device.
At system power-up, the external memory device sends the encrypted configuration
file to the Stratix IV device.
JTAG interface.
Stratix IV device. Encryption of the configuration file is done using the Quartus II
software. The encrypted configuration file is then loaded into the external
memory, such as a configuration or flash device.
10–29:
chapter.
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
CCBAT
pin connection recommendations, refer to the
Stratix IV PowerPlay Early Power
Guidelines.
CCBAT
is at full rail.
© March 2010 Altera Corporation
DC and Switching
Estimator.
Design Security
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