EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 575

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
© March 2010 Altera Corporation
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In other words, when configured for Gen1 data rate and
rx_elecidleinfersel[2:0] = 3'b110, the Electrical Idle Inference module asserts
pipeelecidle high if it does not receive four /K28.5/ COM code groups in a
2000 UI interval. When configured for Gen1 data rate and
rx_elecidleinfersel[2:0] = 3'b111 in the Loopback.Active substate of the
LTSSM state machine, the Electrical Idle Inference module asserts pipeelecidle
high if it does not receive four /K28.5/ COM code groups in a 128 μs interval.
When configured for Gen2 data rate and rx_elecidleinfersel[2:0] = 3'b110,
the Electrical Idle Inference module asserts pipeelecidle high if it does not receive
four /K28.5/ COM code groups in a 16000 UI interval.
The Electrical Idle Inference module does not have the capability to detect the
electrical idle exit condition based on reception of the electrical idle exit ordered set
(EIEOS), as specified in the PCI Express (PIPE) Base Specification.
If you select the Enable Electrical Idle Inference Functionality option in the ALTGX
MegaWizard Plug-In Manager and drive rx_elecidleinfersel[2:0] =
3'b0xx, the Electrical Idle Inference block uses the EIOS detection from the Fast
Recovery circuitry to drive the pipeelecidle signal.
If you do not select the Enable electrical idle inference functionality option in the
ALTGX MegaWizard Plug-In Manager, the Electrical Idle Inference module is
disabled. In this case, the rx_signaldetect signal from the signal detect circuitry in
the receiver buffer is inverted and driven as the pipeelecidle signal.
Recommendation When Using the Electrical Idle Inference Block
In a PCI Express (PIPE) link, when operating at Gen2 data rate, the downstream
device can go into the Disable state after instruction from the upper layer. Once in the
Disable state, the downstream device must detect an Electrical Idle Exit condition to
go into the Detect state. At this same time, the upstream device can be directed by the
upper layer to go into the Detect state and start transmitting the COM symbols to the
downstream device at Gen 1 data rate.
The Disable and Detect states are different states of the Link Training and Status State
Machine as described by the PCI Express (PIPE) Base Specification Rev 2.0.
The COM symbol is an 8B/10B encoded value of K28.5 and is part of the training
sequences TS1 and TS2 as described by the PCI Express (PIPE) Base Specification
Rev 2.0.
When the Stratix IV GX and GT device is operating as a downstream device at
PCI Express (PIPE) Gen 2 data rates and if it goes into the Disable State, the
Stratix IV GX and GT receiver must receive an Electrical Idle Exit condition in order to
move out of the Disable state.
For the Stratix IV GX and GT receiver, the Electrical Idle Exit condition is achieved
when COM symbols are received from the upstream device. However, after the
Disable state is achieved by the Stratix IV GX and GT receiver (the downstream
device) during Gen 2 data rate operation, and if at the same time the upstream device
is directed to transition to the Detect state, the upstream device starts to send COM
symbols at Gen 1 data rate. Consequently, the Stratix IV GX and GT receiver (the
downstream device) does not recognize the COM symbols as it is operating at Gen 2
Stratix IV Device Handbook Volume 2
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