EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 87

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
© November 2009 Altera Corporation
Input
Data
Equation 4–2
(four-multiplier adder).
operation but with a maximum 44-bit accumulation capability by feeding the output
of the unit back to itself, as shown in
Depending on the mode you select, you can bypass all register stages except
accumulation and loopback mode. In these two modes, one set of register must be
enabled. If the register is not enabled, an infinite loop occurs.
To support commonly found FIR-like structures efficiently, a major addition to the
DSP block in Stratix IV devices is the ability to propagate the result of one half block
to the next half block completely within the DSP block without additional soft logic
overhead. This is achieved by the inclusion of a dedicated addition unit and routing
that adds the 44-bit result of a previous half block with the 44-bit result of the current
block. The 44-bit result is either fed to the next half block or out of the DSP block using
the output register stage, as shown in
later sections.
144
Half-DSP Block
provides a sum of four 18 × 18-bit multiplication operations
Equation 4–3
Figure
provides a four 18 × 18-bit multiplication
Figure
4–3.
4–4. Detailed examples are described in
Stratix IV Device Handbook Volume 1
44
Result[]
4–5