EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 349

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Active Serial Configuration (Serial Configuration Devices)
© March 2010 Altera Corporation
1
Upon power-up, the Stratix IV devices go through a POR. The POR delay depends on
the PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T
4 ms < T
low, and tri-states all user I/O pins. After the device successfully exits POR, all the
user I/O pins continue to be tri-stated. If nIO_pullup is driven low during power-
up and configuration, the user I/O pins and dual-purpose I/O pins will have weak
pull-up resistors, which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. After POR, the Stratix IV
device releases nSTATUS, which is pulled high by an external 10-kΩ pull-up resistor
and enters configuration mode.
To begin configuration, power the V
banks where the configuration pins reside) to the appropriate voltage levels.
The serial clock (DCLK) generated by the Stratix IV device controls the entire
configuration cycle and provides timing for the serial interface. Stratix IV devices use
an internal oscillator to generate DCLK. Using the MSEL[] pins, you can select to use a
40 MHz oscillator.
In fast AS configuration schemes, Stratix IV devices drive out control signals on the
falling edge of DCLK. The serial configuration device responds to the instructions by
driving out configuration data on the falling edge of DCLK. Then the data is latched
into the Stratix IV device on the following falling edge of DCLK.
In configuration mode, Stratix IV devices enable the serial configuration device by
driving the nCSO output pin low, which connects to the chip select (nCS) pin of the
configuration device. The Stratix IV device uses the serial clock (DCLK) and serial data
output (ASDO) pins to send operation commands and/or read address signals to the
serial configuration device. The configuration device provides data on its serial data
output (DATA) pin, which connects to the DATA0 input of the Stratix IV devices.
After all the configuration bits are received by the Stratix IV device, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ resistor.
Initialization begins only after the CONF_DONE signal reaches a logic high level. All
AS configuration pins (DATA0, DCLK, nCSO, and ASDO) have weak internal pull-up
resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors. The CONF_DONE
pin must have an external 10-kΩ pull-up resistor in order for the device to initialize.
In Stratix IV devices, the initialization clock source is either the internal oscillator or
the optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Stratix IV device provides itself
with enough clock cycles for proper initialization. You also have the flexibility to
synchronize initialization of multiple devices or to delay initialization with the
CLKUSR option. You can turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General tab of the Device and Pin Options
dialog box. When you select the Enable user supplied start-up clock option, the
POR
POR
< 12 ms. During POR, the device resets, holds nSTATUS and CONF_DONE
< 300 ms. When PORSEL is driven high, the fast POR time is
CC
, V
CCIO
, V
CCPGM
, and V
Stratix IV Device Handbook Volume 1
CCPD
voltages (for the
10–17