EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 625

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Table 1–68. FPGA Fabric-PMA Interface Widths and Data Rates Supported in Basic (PMA Direct) ×1/×N Single-Width and
Double-Width Modes for Stratix IV GX and GT Devices
© March 2010 Altera Corporation
Functional Mode
×1/×N
Single-width
mode
×1/×N
Double-width
mode
(PMA Direct)
Basic
f
f
f
Interface Width
Fabric-PMA
Table 1–68
supported in Basic (PMA Direct) ×1/×N single-width and double-width modes.
Basic (PMA Direct) ×1 Configuration
You can configure a transceiver channel in this mode by setting the which protocol
will you be using? field to Basic (PMA Direct) and the which sub protocol will you
be using? field to none. In this configuration, the Quartus II software requires one of
the two CMU PLLs within the same transceiver block to provide high-speed clocks to
the transmitter side of the channel.
If the CMU0 or CMU1 channel is configured in Basic (PMA Direct) ×1 configuration, use
their local clock dividers to provide clock to their respective transmitter channels.
For information about clocking restrictions in Basic (PMA Direct) ×1 mode, refer to
the “Non-Bonded Basic (PMA Direct) Mode Channel Configurations” section in the
Stratix IV Transceiver Clocking
For information about routing the clocks to transceiver channels in Basic
(PMA Direct) ×1 mode, refer to the
Basic (PMA Direct) ×N Configuration
You can configure a transceiver channel in this mode by setting the which protocol
will you be using field to Basic (PMA Direct) and the which sub protocol will you
be using field to ×N. In this mode, all the transmitter channels can receive their
high-speed clock from the CMU0 PLL from the transceiver blocks or the ATX PLL
present on the same side of the device. These clocks are provided through the ×N_Top
or ×N_Bottom clock line.
In this mode, if you use a CMU PLL to generate the transceiver channel datapath
interface clocks, only the CMU0 central clock divider of the transceiver block
containing the CMU PLL is used.
For information about clocking restrictions in Basic (PMA Direct) ×N mode, refer to
the “Non-Bonded Basic (PMA Direct) Mode Channel Configurations” section in the
Stratix IV Transceiver Clocking
10 bit
16 bit
20 bit
FPGA
8 bit
lists the Stratix IV GX and GT PLD-PMA interface widths and data rates
C2 Speed Grade
0.6Gbps to
0.6Gbps to
1.0Gbps to
1.0Gbps to
3.25Gbps
2.6Gbps
5.2Gbps
6.5Gbps
chapter.
chapter.
C3/I3 Speed Grade
Stratix IV GX
Stratix IV Transceiver Clocking
0.6Gbps to
0.6Gbps to
1.0Gbps to
1.0Gbps to
3.25Gbps
2.6Gbps
5.2Gbps
6.5Gbps
Supported Data Rate Range
C4 Speed Grade
0.6Gbps to
0.6Gbps to
1.0Gbps to
1.0Gbps to
3.25Gbps
2.6Gbps
5.0Gbps
5.0Gbps
Stratix IV Device Handbook Volume 2
chapter.
2.488 Gbps to
2.488 Gbps to
2.488 Gbps to
2.488 Gbps to
Stratix IV GT
3.25 Gbps
I1, I2, I3
2.6 Gbps
5.2 Gbps
6.5 Gbps
1–187