EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 36

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–18
Table 1–9. Stratix IV GT Device On-Package Decoupling Information
Integrated Software Platform
Stratix IV Device Handbook Volume 1
EP4S40G2F40
EP4S100G2F40
EP4S100G3F45
EP4S100G4F45
EP4S40G5H40
EP4S100G5H40
EP4S100G5F45
Notes to
(1)
(2) For I/O banks 3(*), 4(*), 7(*), and 8(*) only. There is no OPD for I/O bank 1(*), 2(*), 5(*), and 6(*).
Information
Ordering
Table 1–9
devices, contact
Table
refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
1–9:
Altera Technical
Table 1–8
Table 1–8. Stratix IV GT Device Package Options
Table 1–9
The Quartus II software provides an integrated environment for HDL and schematic
design entry, compilation and logic synthesis, full simulation and advanced timing
analysis, SignalTap II Logic Analyzer, and device configuration of Stratix IV designs.
The Quartus II software provides the MegaWizard
generate different functional blocks, such as memory, PLL, and digital signal
processing logic. For transceivers, the Quartus II software provides the ALTGX
MegaWizard Plug-In Manager interface that guides you through configuration of the
transceiver based on your application requirements.
2× 470 nF
4× 470 nF
2× 1 uF +
4× 1 uF +
Stratix IV GT 40 G Devices
EP4S40G2
EP4S40G5
Stratix IV GT 100 G Devices
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
Notes to
(1) Devices under the same arrow sign have vertical migration capability.
(2) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information,
(3) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm × 42.5-mm Hybrid flip chip
V
CC
refer to the
packages.
Support.
Table
summarizes the resource counts for the Stratix IV GT devices.
lists the Stratix IV GT on-package decoupling information.
Device
1–8:
Altera Device Package Information Data
10 nF per bank
10 nF per bank
V
CCIO
(2)
(2)
transceiver block
transceiver block
(40 mm × 40 mm)
100 nF per
100 nF per
V
1517 Pin
CCL_GXB
(Note 1)
H40
H40
F40
F40
Sheet.
—
—
(Note 1)
(3)
(3)
(2)
™
Plug-In Manager user interface to
Chapter 1: Stratix IV Device Family Overview
100 nF
100 nF
V
CCA_L/R
© March 2010 Altera Corporation
(45 mm × 45 mm)
Integrated Software Platform
100 nF
100 nF
V
CCT_L/R
1932 Pin
F45
F45
F45
—
—
—
100 nF
100 nF
V
CC R_L /R