EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 733
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 2: Stratix IV Transceiver Clocking
FPGA Fabric-Transceiver Interface Clocking
© March 2010 Altera Corporation
Figure 2–37. Sixteen Identical Channels Across Four Transceiver Blocks for Example 8
Common Clock Driver Selection Rules
The common clock driver driving the rx_coreclk ports of all channels must have a
0 PPM frequency difference with respect to the receiver phase compensation FIFO
write clocks of these channels. If there is any frequency difference between the FIFO
read clock (rx_coreclk) and the FIFO write clock, the FIFO overflows or
under-runs, resulting in corrupted data transfer between the FPGA fabric and the
receiver.
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Status
and Status
and Status
RX Data
and Status
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
Fabric
FPGA
rx_coreclk[15:12]
rx_coreclk[11:8]
rx_coreclk[3:0]
rx_coreclk[7:4]
Clock Driver
Common
rx_clkout[7:4]
rx_clkout[3:0]
rx_clkout[15:12]
rx_clkout[11:8]
Transceiver Block GXBR3
Transceiver Block GXBR1
Transceiver Block GXBR2
Transceiver Block GXBR0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Stratix IV Device Handbook Volume 2
2–69
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