EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 346
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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10–14
Figure 10–5. FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled
Notes to
(1) Use this timing waveform when you have enabled the decompression and/or design security features.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(3) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT. The state of these pins depends on
(7) If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to
Table 10–5. FPP Timing Parameters for Stratix IV Devices with the Decompression and/or Design Security Features Enabled
Stratix IV Device Handbook Volume 1
t
t
t
t
t
t
t
t
t
(Note
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CONF_DONE
When nCONFIG is pulled low, a reconfiguration cycle begins.
the dual-purpose pin settings.
sending the first DCLK rising edge.
nSTATUS (3)
INIT_DONE
DATA[7..0]
1),
nCONFIG
Figure
User I/O
(2)
DCLK
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
(4)
10–5:
(Part 1 of 2)
t
t
CFG
CF2CD
t
CF2ST1
t
Figure 10–5
device as an external host. This waveform shows the timing when you have enabled
the decompression and/or design security features.
Table 10–5
when you enable the decompression and/or the design security features.
CF2ST0
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
Parameter
1
2
Byte 0
t
lists the timing parameters for Stratix IV devices for FPP configuration
DH
shows the timing waveform for FPP configuration when using a MAX II
3
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
4
1
t
CH
2
t
Byte 1
CLK
t
t
CL
DH
3
4
Stratix IV
3/(DCLK frequency) + 1
(6)
(7)
Minimum
500
—
—
10
—
2
2
4
Byte 2
1
Stratix IV
(7)
Byte (n-1)
3
Stratix IV
4
(6)
© March 2010 Altera Corporation
Byte n
Maximum
500
500
Fast Passive Parallel Configuration
t
CD2UM
800
800
—
—
—
—
—
(3)
(3)
Stratix IV
(7)
(5)
(6)
(Note
User Mode
User Mode
1),
Units
μ s
ns
ns
ns
ns
(2)
μ s
μ s
μ s
μ s
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