EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 924
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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5–88
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 11 of 13)
Stratix IV Device Handbook Volume 2
reconfig_data[15:0]
reconfig_address[5:0]
rate_switch_ctrl[1:0]
rate_switch_out[1:0]
logical_tx_pll_sel
logical_tx_pll_sel_en
channel_reconfig_done
Port Name
Output
Output
Input/
Input
Input
Input
Input
Input
Input
This signal is applicable only in the dynamic reconfiguration modes
grouped under the Channel and TX PLL select/reconfig option.
This is a 16-bit word carrying the reconfiguration information. It is
stored in a .mif that you must generate. The ALTGX_RECONFIG
instance requires that you provide reconfig_data [15:0]on
every .mif write transaction using the write_all signal.
This port is available for selection only in the .mif-based
transceiver channel reconfiguration modes.
For more information, refer to
page
This signal is available when you select data rate division in
transmitter mode. Based on the value you set here, the divide-by
setting of the local divider in the transmitter channel gets modified.
The legal values for this port are:
2’b00 = Divide by 1
2’b01 = Divide by 2
2’b10 = Divide by 4
2’b11 = Not supported
This signal is available when you select data rate division in
transmitter mode. You can read the existing local divider settings of
a transmitter channel at this port. The decoding for this signal is
listed below:
2’b00 = Division of 1
2’b01 = Division of 2
2’b10 = Division of 4
2’b11= Not supported
At this port you specify the identity of the transmitter PLL you want
to reconfigure. You can also specify the identity of the transmitter
PLL that you want the transceiver channel to listen to. When you
enable this signal, the value set at this signal overwrites the
logical_tx_pll value contained in the .mif. The value at this
port must be held at a constant logic level until reconfiguration is
done.
If you want to use the logical_tx_pll_sel port only under
some conditions and use the logical_tx_pll value contained
in the .mif otherwise, enable this optional
logical_tx_pll_sel_en port. Only when
logical_tx_pll_sel_en is enabled and set to 1 does the
dynamic reconfiguration controller use logical_tx_pll_sel
to identify the transmitter PLL. The value at this port must be held
at a constant logic level until reconfiguration is done.
This signal goes high to indicate that the dynamic reconfiguration
controller has finished writing all the words of the .mif. The
channel_reconfig_done signal is automatically de-asserted
at the start of a new dynamic reconfiguration write sequence. This
signal is applicable only in channel and CMU PLL reconfiguration
and channel reconfiguration with transmitter PLL select modes.
5–23.
Chapter 5: Stratix IV Dynamic Reconfiguration
Description
Dynamic Reconfiguration Controller Port List
“Reduced .mif Reconfiguration” on
© March 2010 Altera Corporation
(Note
3),
(4)
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