EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 56

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–16
Figure 2–14. Register Chain within the LAB
Note to
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.
Stratix IV Device Handbook Volume 1
Figure
2–14:
For more information about register chain interconnect, refer to
on page
Combinational
Combinational
Logic
Logic
2–17.
(Note 1)
adder0
adder1
adder0
adder1
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
reg_chain_out
reg_chain_in
labclk
D
D
D
D
reg0
reg1
reg0
reg1
From previous ALM
within the LAB
To next ALM
within the LAB
Q
Q
Q
Q
© November 2009 Altera Corporation
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
“ALM Interconnects”
Adaptive Logic Modules