EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 481
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Table 1–21. Settings for a Stratix IV GX to Stratix II GX DC-Coupled Link
© March 2010 Altera Corporation
600-6375 Mbps
Note to
(1) V
Data Rate
CCH
Table
= 1.5 V can support data rates from 600 Mbps to 6.5G Mbps. V
1–21:
Transmitter (Stratix IV GX) Settings
1.4/1.5 V
V
CCH
Figure 1–36
(PCML) DC-coupled link.
Figure 1–36. Stratix IV GX Transmitter (PCML) to Stratix II GX Receiver (PCML)
Note to
(1) R
Table 1–21
transmitter (PCML) to Stratix II GX receiver (PCML) DC-coupled link.
(1)
S
is the parasitic resistance present in the on-chip RX termination and biasing circuitry.
Figure
42.5/50/60/75-
TX Termination
TX V
0.65 V
shows the allowed transmitter and receiver settings in a Stratix IV GX
1–36:
shows the Stratix IV GX transmitter (PCML) to Stratix II GX receiver
Stratix IV GX
Transmitter
CM
V
CCH
= 1.4/1.5 V
Ω
100/120/150 Ω
Termination
Differential
TX
V
CM
42.5/50/60/75-
TX Termination
0.65 V
CCH
Physical Medium
Physical Medium
= 1.4 V can support data rates from 600 Mbps to 6375 Mbps.
600-6375 Mbps
Data Rate
Ω
50/60/75-
RX Termination
Receiver (Stratix II GX) Settings
Ω
Standard
1.4/1.5 V
PCML
I/O
RX
V
CM
Stratix IV Device Handbook Volume 2
R
s
0.85 V
50/60/75-
RX Termination
(1)
RX V
0.85 V
Stratix II GX
Receiver
Ω
CM
100/120/150 Ω
Termination
Differential
1–43
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