EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 72
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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3–14
Figure 3–13. True Dual-Port Timing Waveform
Stratix IV Device Handbook Volume 1
q_a (asynch)
q_b (asynch)
address_a
address_b
data_a
wren_a
wren_b
clk_a
clk_b
din-1
an-1
doutn-1
Table 3–8. M144K Block Mixed-Width Configurations (True Dual-Port Mode) (Part 2 of 2)
In true dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output “new data” at that location or “old data”. To choose the desired
behavior, set the read-during-write behavior to either new data or old data in the
RAM MegaWizard Plug-In Manager in the Quartus II software. For more information,
refer to
In true dual-port mode, you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. No conflict resolution circuitry is built into the
Stratix IV TriMatrix memory blocks. You must handle address conflicts external to the
RAM block.
Figure 3–13
and the read operation at port B, with the Read-During-Write behavior set to new
data. Registering the RAM’s outputs simply delays the q outputs by one clock cycle.
16K × 9
8K × 18
4K × 36
bn
din-1
Read Port
“Read-During-Write Behavior” on page
din
an
shows true dual-port timing waveforms for the write operation at port A
doutn
din
b0
a0
16K × 8
dout0
—
—
—
a1
dout0
dout1
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
8K × 16
b1
—
—
—
a2
dout2
4K × 32
a3
—
—
—
3–18.
Write Port
dout3
dout1
b2
din4
a4
16K × 9
v
v
v
© March 2010 Altera Corporation
din4
din5
a5
8K × 18
v
v
v
dout2
din5
b3
din6
a6
Memory Modes
4K × 36
v
v
v
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