EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 785
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 3: Configuring Multiple Protocols and Data Rates in a Transceiver Block
Combining Transceiver Channels with Basic (PMA Direct) Configuration
© November 2009
Altera Corporation
In this case, the ATX PLL provides the high-speed clock to the transmitter channel of
inst 1. Therefore, you can combine 10 channels of inst 0 and one channel of
inst 1 in two transceiver blocks, as shown in
Figure 3–21. Combining Basic (PMA Direct) ×N Configuration with Non-Basic (PMA Direct)
Configuration Using an ATX PLL for Example 10
Notes to
(1) The ATX PLL provides the high-speed clock to channel 0 of inst1.
(2) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents
the ×N bottom clock line.
Figure
3–21:
Base data rate
ATX PLL
5 Gbps
CMU0
CMU0 Channel
PLL
RX
RX
RX
RX
RX
Inst0: Channel 0
RX
RX
RX
RX
RX
ATX PLL block
Inst0: Channel 4
RX
Inst0: Channel 1
Inst0: Channel 2
Inst0: Channel 5
Inst0: Channel 8
Inst0: Channel 3
Inst0: Channel 6
Inst0: Channel 7
Inst0: Channel 9
Inst1: Channel 0
GXBR0
GXBR1
TX
TX
TX
TX
TX
Central
Divider
TX
TX
TX
TX
TX
Clock
TX
Central
Divider
Clock
(Note 1)
Figure 3–21
x4 Clock Line (2)
xN Bottom Clock Line (2)
xN Top Clock Line (2)
Stratix IV Device Handbook Volume 2
3–39
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