EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 514

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–76
Figure 1–56. Rate Match Deletion in PCI Express (PIPE) Mode
Figure 1–57. Rate Match Insertion in PCI Express (PIPE) Mode
Stratix IV Device Handbook Volume 2
pipestatus[2:0]
dataout
pipestatus[2:0]
datain
dataout
datain
3'b001
K28.5
K28.5
First Skip Ordered Set
The rate match FIFO inserts or deletes only one SKP symbol per SKP ordered set
received. Rate match FIFO insertion and deletion events are communicated to the
FPGA fabric on the pipestatus[2:0] port from each channel. The
pipestatus[2:0] signal is driven to 3'b001 for one clock cycle synchronous to the
/K28.5/ COM symbol of the SKP ordered set in which the /K28.0/ SKP symbol is
inserted. The pipestatus[2:0] signal is driven to 3'b010 for one clock cycle
synchronous to the /K28.5/ COM symbol of the SKP ordered set from which the
/K28.0/ SKP symbol is deleted.
Figure 1–56
SKP symbols are required to be deleted. Only one /K28.0/ SKP symbol is deleted per
SKP ordered set received.
Figure 1–57
symbols are required to be inserted. Only one /K28.0/ SKP symbol is inserted per
SKP ordered set received.
The rate match FIFO full and empty conditions are communicated to the FPGA fabric
on the pipestatus[2:0] port from each channel.
The rate match FIFO in PCI Express (PIPE) mode automatically deletes the data byte
that causes the FIFO to go full and drives pipestatus[2:0] = 3'b101
synchronous to the subsequent data byte.
3'b010
K28.5
First Skip Ordered Set
K28.5
K28.0
K28.0
xxx
shows an example of rate match deletion in the case where two /K28.0/
shows an example of rate match insertion in the case where two SKP
K28.0
K28.0
Dx.y
Dx.y
xxx
xxx
Second Skip Ordered Set
K28.5
Dx.y
xxx
3'b010
K28.5
Dx.y
SKIP Symbol Deleted
3'b001
K28.5
K28.0
Second Skip Ordered Set
SKIP Symbol Inserted
K28.0
K28.5
xxx
K28.0
K28.0
xxx
K28.0
K28.0
xxx
K28.0
K28.0
Chapter 1: Stratix IV Transceiver Architecture
xxx
K28.0
K28.0
K28.0
K28.0
xxx
xxx
© March 2010 Altera Corporation
Transceiver Block Architecture
K28.0
xxx
K28.0
K28.0
xxx